Debugging Patterns with Protocols
Which register is being written? Vector 21245 is set to zero, let me check, must be bit 5 of the register, bit is active low, so therefore the regulator is enabled. But wait, is it MSB or LSB first? And is what is the address? If you are a semiconductor test engineer, this probably sounds all too familiar. Verifying pattern contents is a manual, time consuming and tedious process. Large number of vector repeats make even simple protocols difficult to interpret. Unfortunately, the chip will not tell you what is wrong with your pattern.
Thankfully there are ways to have a computer do the work for you. In this blog post, I will show how to convert an pattern to a Verilog Testbench using Test Insight’s Virtual Tester. With the output data, I’ll put it through an open-source waveform viewer, PulseView with a protocol decoder that in plain text (I should really say, plain hex) what the pattern is doing.
Virtual Tester works with different platforms, I’m on Advantest 93k so that is what is used in this example. If you are creating your own patterns on the tester, e.g. with SmartVec, this is even more useful for saving hours of debugging time.
A Way Out
The tester’s environment is good for controlling the instruments, but less suited to integrate with other tools. One of the recurring challenges in my work relates exactly to this - how can you know that the tester is doing what you think? When working on wafer test, there is no easy way to get to the pins to measure. And as often, if you are logging in to a remote OSAT, all you have is your screen and keyboard.
TestInsight’s Virtual Tester converts all timing information and pattern contents into Verilog code. This means that you have the exact timing information coupled with the pattern contents in a form that you can simulate. Once you escape from the tester environment, there is a wealth of opportunities for further debug, optimization and analysis.
This Example
In this example, I will use Virtual Tester to decode I2C. I2C is perhaps not the most thrilling protocol to work with, but it serves very well as an example. The process has three steps:
Export pattern and timing from Advantest 93k SmarTest program using Virtual Tester
Simulate the generated Verilog code to produce a VCD or CSV output
Use protocol decoder in PulseView to check what is going on.
I have created a small testprogram, for Advantest 93k SmarTest 7. It has a pattern that I created for this example, which contains an I2C write and I2C read operation. Now this pattern has a large number of repeats so it is quite tedious to read out its contents manually. If you’re on the 93k, you have probably learned to love the blue timing diagram - it really is a great thing despite its age (83k?) but it will not decode your pattern.
SmarTest Pattern and Timing Diagram View
Virtual Tester Config
The easiest possible config uses three lines. Virtual Tester needs to know
Path to test program: _93k _testdir
Testflow name: _93k_testflow
Test Suite Name (or names, takes a list): _93k _testsuites
As you have probably seen, the setup file is in Python! This is a nice surprise since it’s the third most widespread language in the world. Lists, strings etc are handled the usual way.
To generate a template config file, use ./93kvt -template
Virtual Tester Config File
When you are happy with the configfile, run
93kvt -setup <filename.py>
We now get this:
VT Typical Output
Verilog Simulation
There are quite a few files being produced by Virtual Tester but we also get the compile information inside vtrun1 and vtrun2. In my case, I have used ModelSim but this setup varies between different simulators - see the code on github for details.
The simulation transcript is used to output a CSV-file that I load into Pulseview.
PulseView with I2C Decoder
And look! Selecting the I2C decoder, our pattern is decoded. It correctly picks up start- and stop conditions, address, read and write of data.
Successful I2C Write Operation
Successful I2C Read Operation
The example code,
Minimal 93k Testprogram
Virtual Tester Configuration
Script for running the simulation
is on GitHub.